Digital-to-analog converters convert digital words into analog values, such as analog voltage values or analog current values. When the digital word consists of n bits, the corresponding analog value may be generated by applying progressive power of two weightings to each of the n bits.
Conventional resistor network digital-to-analog converters use a network of resistor stages to apply the progressive weightings to each bit. Known resistor network digital-to-analog converters include, for example, binary weighted digital-to-analog converters and R/2R ladder digital-to-analog converters. These conventional resistor network digital-to-analog converters sample each bit at a reconstruction clock frequency, fs, and apply those sampled bit values to progressively weighted resistor stages. Each of these stages, however, introduces reconstruction error into the analog output signal in the form of both static error and transient error (e.g. noise spikes).
Increasing fs has the advantage of moving these reconstruction errors introduced by the resistor network to a higher frequency, thereby relaxing the design requirements for filtering out those reconstruction errors. This increase, however, results in the digital-to-analog converter consuming more power. The higher power consumption may be unacceptable in low power applications, such as mobile communication devices.